VexRISC-V Exposed

Hackaday
VexRISC-V Exposed
VexRISC-V Exposed

If you want to use FPGAs, you’ll almost always use an HDL like Verilog or VHDL. These are layers of abstraction just like using, say, a C compiler is to machine language or assembly code. There are other challenges to the throne such as SpinalHDL which have small but enthusiastic followings. [Tom] has a post about how the VexRISC-V CPU leverages SpinalHDL to make an extremely flexible system that is as efficient as plain Verilog. He says the example really shows off why you should be using SpinaHDL.

Like a conventional programming language, it is easy to find niche languages that will attract a little attention and either take off (say, C++, Java, or Rust) or just sort of fade away. The problem is you can’t ever tell which ones are going to become major and which are just flashes in the pan. Is SpinalHDL the next big thing? We don’t know.

[Tom] is pretty qualified to write this, too. He had a RISC-V design, MR1, and in comparisons, the SpinalHDL implementation was better. He wanted to know why. The post is a result of his exploration.

SpinalHDL uses Scala — an object-oriented programming language and is really a set of libraries that generates HDL. That means you wind up with Verilog or VHDL that you handle with your normal tools or you can even mix it in with conventional modules. The language proponents claim that using it generates efficient HDL that won’t cause your design to be slower or larger.

Is it worth switching? We don’t know. Is it worth a look? Probably. We actually looked at VexRISC-V recently, but not in this much detail. If you don’t like Scala, but like the approach, MyHDL is sort of like SpinalHDL but based on Python.

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VexRISC-V Exposed